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Stephen
Douglas Craven's Research Page |
Soft processors are processors constructed out of the configurable logic in an FPGA or CPLD. Popular soft processors include the Xilinx MicroBlaze, Altera Nios II, OpenRISC, and Leon 2. While any processor can be tailored to its individual application, forming an Application-Specific Instruction set Processor (ASIP), the customization process is much more straightforward for a soft processor as the configurable nature of FPGAs allows for rapid prototyping and implementation. Configurable soft processor arrays are arrays of ASIPs created in an FPGA.
Motivation
The motivation for creating configurable processor arrays stems from two growing trends in computer engineering: Single Chip MultiProcessors (SCMP) and Application-Specific Instruction set Processors (ASIP).
Approach
The approach we are considering is to first map the application to an array of processors connected by simple interfaces.
The motivation for creating configurable processor arrays stems from two growing trends in computer engineering: Single Chip MultiProcessors (SCMP) and Application-Specific Instruction set Processors (ASIP).
Approach
The approach we are considering is to first map the application to an array of processors connected by simple interfaces.
The processors are then optimized
through a variety of techniques including instruction removal,
instruction set extension, datapath sizing, and storage element
sizing. Each optimization aims to either increase the throughput
of a given node or decrease its size, allowing additional processors to
be added to the array.
The simple interfaces between
processors remain untouched, facilitating processor optimization.
In the extreme case, the processor can be completely replaced with a
custom datapath, with the interface and interaction between processing
elements remaining unchanged.
Presentations
Military and Aerospace Programmable Logic Devices (MAPLD) 2005 conference presentation discussing the OpenFire processor:
openfire_mapld.ppt (474kB)
Virginia Tech Computer Engineering weekly seminar (9/30/2005) discussing a configurable array design methodology:
craven_cpe_seminar.ppt (1.5MB)