Notes on research for the DRACS project in the CCM lab at Virginia Tech.
We have some images of the board and our fixes.
First the hardware. We use a 1 wire (yes 1) serial console. Hook a wire from pin 3 (?) to the serial port pin 2 as shown below:
10 [ o] 9 [o o] P3 [o o] [o o]<------ 2 [o o] 1
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v
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\ o o o o o /
\ o o o o /
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Some environment variables need to be setup. Source the startup script with the following command for bash:
$ source /rcm/startup.shand for
c-shell:
$ source /rcm/startup.csh
The PATH should now have other scripts in
"/rcm/rcm/scripts/",
tools in
"/rcm/rcm/tools/",
and Python scripts in
"/rcm/rcm/tests/".
Here's the sequence we use to start things up. In one terminal run minicom:
(1) $ minicomIn another run the following:
(2) $ cd /rcm/rcm (3) $ ./scripts/RCMReload (4) $ ./tools/RCMConfigXilinx ./fpga/current/fpga.bit (5) $ ./tests/freeclkAfter which you should be able to run the ACS demos. (let us know if this doesn't work)
(1) Starts up the serial monitor.
(2) Just so the following paths work. Feel free to change paths as needed.
(3) Runs some commands to load and start the RCMOS on the PowerPC
(4) Loads the bitstream on the Xilinx FPGA. This logic acts as the interface between the CSRC, FIFO, and the PowerPC.
(5) This is a little bit of Python that flips some bits in the FPGA so that CSRC clock is enabled other than when the FIFOs have data in them. Required in order to switch contexts (since that process needs the clock) and hence a major part of configuring the chips. Poor name, poor behavior, will likely be fixed later.
All these command tools and others can be found in the "tools/" directory. The command names are intuitive enough to make out the functionality. Any command can be run without any parameters to get a brief format of the command with the parameters.
Now any hex file can be loaded onto the CSRC by the command:
(6) $ ./tools/RCMConfigCSRC
Since I (dave) like Python I wrote some bindings to librcm and a bunch of scripts. The code is all in the "python/" and "tests/" directories.
There is an object-oriented wrapper around the whole board. Take a look at the tests to see how it works. Also, PyUnit is used to create a test framework for the board using the bindings. All in the tests dir. The hexfiles are not in the dist (yet) so some of the tests will certainly fail. alltests.py should test some basic functionality of the board after the RCMOS and Xilinx config are loaded.
Unless you happen to have all (user from fpga and hardwired) clocks running at same freq you will get a combined signal. We had a low freq clock dominating a high freq one. This really confused the FIFOs.
The output of U36 is controled via FPGA_CLKIN2 which also controls CSRC, memory, and other clocks. We determined the intent is to have U36 drive FIFO_OUT_WCLK so that FIFO_IN_RCLK, CSRCs, and FIFO_OUT_WCLK are all synced.
Convieniently you can fix this by just popping off R59 which may or may not be covered by rework wires. (just push them aside)
Here's what it should look like. Notice the removed resistor in the middle of the image right above the E15 text. Here's what it looks like on another board... we had to push those wires aside to get to the resistor.
1. Connect pin OA5 of U36 (49FCT805) to B4 (K) pin of U11/U10 (SRAM)
2. Connect pin OA4 of U36 (49FCT805) to B4 (K) pin of U8/U9 (SRAM)
3. Connect pin OB5 of U36 (49FCT805) to B4 (K) pin of U6/U7 (SRAM)
4. Connect pin OB3 of U36 (49FCT805) to B4 (K) pin of U4/U5 (SRAM)
The board as shown in the schematic has the K pins of the memory connected to the CSRC pins CSRCA/B_BANK1/2_K. CSRC clock can't be driven on to these pins. Clock has to be generated by explicit Hi/Low on these pins. So the clock for memory is atleast half that of the CSRC clocks. To over come this the above modifications are made. Be sure not to drive any signal on to these CSRCA/B_BANK1/2_K pins.
Here is a crude CSRC memory model which can be used for simulating the memory. I'll add some more features to it later.
Excuse the rough ascii diagram. This is the back of the board with links to images I'm too lazy to stich together.
+--------+
|#### |
| # |
| |
+-----|||+
PCI
If you look at the data sheet you will notice that there is a section about width expansion. It specifcally notes that you need to gate some of the flags. This is not on our board and it looks like we would have to do some fancy rework to fix it. I'd rather not. We may never notice this problem assuming the timing is "Just Right"®. But beware that streaming could have some strange errors where the top half of the bits are one entry off the lower half. Yuck.
just ask...
The FIFO spec sheet is no longer online since the IDT has discontinued production of the older part we have. Here is the spec sheet for the old part.
Quick tour of where stuff is in case you happen to be someone who needs to know.
You may download the image file of VTDRACS environment by click this.