Janus
Compiler for Run Time Reconfiguring Applications

The Java based Hardware Description Language: JHDL


JHDL is a language developed with the intent of elegantly embodying the run-time reconfiguration paradigm in a commonly used (familiar) programming environment. This approach allows the user to describe, netlist, simulate, and execute full run-time reconfigurable systems, all with a single Java description. Java is used to implement a simulation kernel that models hardware execution with a set of classes such as "Wire", "Synchronous", "CombinationalLogic", and so forth. The dynamic creation/destruction of these objects is exploited to model run-time hardware reconfiguration. Furthermore, the component classes provide built-in hierarchical netlisting. Finally, the system is bundled into wrapper classes that can either perform the computation by running the simulation kernel, or by making device driver calls to load a corresponding circuit into an FPGA system. Thus, software simulation and hardware execution are performed with the same piece of code, enabling a true codesign methodology.
 
The primary objective of this research project is to develop a tool-suite/design-environment for describing configurable computing applications that merges the circuit description and the control program into a single, integrated piece of software. This project has the following additional requirements and potential benefits:
  • It must use an existing programming language with no extensions. This will make the tool accessible to a wider range of programmers by allowing them to use commercially-available compilers.
  • The CCM-control paradigm must be CCM independent. CCM control details should be abstracted to a higher level programming abstraction. This will make CCMs more accessible to programmers and will also ease the process of retargetting an applications to run on a variety of different CCMs.
  • The description method must support run-time and partial configuration. These are the most demanding CCM applications and will be used from the outset to stress the design environment.
  • The integrated description must serve for both simulation and final execution with no modifications. For simulation, it must support end-to-end simulation of applications that may consist of many configurations.

    • For execution, it should be possible to switch transparently from a software simulation to hardware execution on the CCM simply by changing a software switch.

    JHDL Approach

     
    The primary distinction of JHDL and indeed the primary goal of this project is the creation of a single integrated API that allows the designer to express circuit organizations that dynamically change over time. Stated another way, the primary goal is to allow the designer to specify, in a reasonably natural way, when hardware gets loaded and removed from a CCM without exposing any of the details normally associated with CCM operation. Rather than invent a new language feature to schedule the configuration of circuits, we chose to adopt the object-instance construction/destruction mechanism used in object-oriented languages.
     
    The current JHDL system is implemented as a set of Java class libraries with functionality divided into two basic areas: circuit simulation and CCM runtime support. Circuit simulation classes allow the designer to design circuit models that can be simulated at the clock level through the JHDL simulation kernel. CCM runtime support classes provide transparent access to CCM control functions via the construction/destruction mechanism. Designers develop circuits in JHDL by selecting from a set of synchronous and combinational elements and wiring these together to form any arbitrary synchronous circuit. There are three different classes that can be used to implement a circuit: CL (combinational), Synchronous (clocked), and Structural (interconnection of combinational or synchronous elements). When creating a new circuit, the designer decides whether the outputs of the circuit are updated continuously, i.e., it is a combinational circuit (a CL object), or are updated only on a clock edge, i.e., it is a synchronous circuit (a Synchronous object), or if it is a structural circuit (Structural object), i.e., one that is just a set of existing synchronous or combinational circuit elements interconnected together. In each case, the designer defines a new class that inherits from the appropriate class and implements the desired functionality in the constructor and other methods. Individual circuits are interconnected by instantiating Wire objects and passing these to the object as arguments to the object constructors.

    JHDL Examples

    JHDL has been used to describe and execute several "real" applications, such as the "shapesum" and "correlation" functions of the Chunky-SLD Automatic Target Recognition (ATR) problem. These applications have been implemented on the Xilinx 6200 using partial reconfiguration, as well as on other platforms. For this initial feasibility study, the original circuits are being used as they were originally implemented via schematic capture and manual placement. The main difference is that the entire circuit is now described in JHDL. This description provides a comprehensive simulation model of the ATR application.

    Benefits and Progress of JHDL

  • JHDL is based on a popular language and requires no language extensions for circuit design.
  • The CCM control paradigm is CCM independent, adopting the object-instance construction metaphor from object-oriented languages. The abstraction will work with any standard CCM.
  • JHDL supports both partial and global configuration and demonstration applications from ATR have been implemented to show this capability.
  • A JHDL application description serves as both simulation and execution for CCM applications. No code modifications are required and switching between software simulation and hardware execution on the CCM requires the setting of a single boolean variable.

    • For more information on the JHDL tools go to the JHDL home page at http://www.jhdl.org