Selected Publications
Jorge Suris, Peter Athanas, Cameron Patterson, "An Efficient Run-Time Router for Connecting Modules in FPGAs", Proceedings of the 2008 International Conference on Field Programmable Logic and Applications, FPL 2008, Heidelberg, Germany, Sep 2008.
Abstract:
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents a dynamic router for Xilinx FPGAs, designed to run on stand-alone embedded systems. With information obtained from Xilinx's XDL tool, a compact routing database for the Virtex-II/IIP/4 devices is built which only requires 96 KB of storage. A channel routing algorithm is used because of its deterministic execution time and because all routing resources in the channel are available. Sample channels are routed with the router and compared with the Xilinx PAR tool. Improvements in both execution time and in memory usage of several orders of magnitude are observed.
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