Design of a direct conversion AM receiver

A direct conversion receiver is proposed because of its simplicity of implementation, and is presented in Figure 1. As this simple design lacks an automatic gain control (AGC) stage, the listening level of stations will depend on the power level received at the antenna. Detailed specifications are given in order to help determine the parameters required at the PIM, and the information that should be present in the mapping file. The designed blocks are plattform specific to the Xilinx Virtex 4 FPGA.

Figure 1. Block diagram of the proposed AM receiver.

Design

The following are the FCC specifications for AM radio stations in the US:

• Carrier frequency: 525 - 1705 KHz
• Channel bandwidth: 10 kHz
• Modulation index (μ): 85 to 95%
• Audio response: 100 Hz - 5 kHz ± 2dB

The system design parameters for a Xilinx Virtex 4 FPGA are the following:

• System clock frequency: 200 MHz
• Sampling frequency: 4 MHz
• Bit precision at the modules: 16 bits. All the modules are designed using Xilinx' Core Generator.

NCO Design

The numerical controlled oscilator (or direct frequency sinthesizer, DSS) is designed in Core Generator using the following parameters:

• Function: Sine and cosine
• DDS Clock Rate: 4 MHz
• Spourious Free Dynamic Range: 42 dB
• Frequency Resolution: 2 Hz
• Number of channels: 1
• Handshaking: RDY and RFD pins on.
• Pipelining: on

The design summary indicates an output width of 8 bits, data width of 21 bits and latency of 2 clock cycles. These values are outputs of the tool.

Multiplier design

Considering the sine and cosine bit width of 7 bits and the ADC width of 14 bits (implying a 20 bit output in signed arithmetic), a paralell multiplier is designed to output the 16 most significant bits (bits 20:5).

Decimating filter design

Band pass filter zero is required due to limitations on the hardware lowpass filters at the laboratory. As the lowest cuttoff frequency filter in the lab is at 5 MHz, a sampling frequency of 12 MHz is chosen at the system input. A Matlab m-file was created to receive the user specifications and generate the coefficients (.coe) file required by Core Generator for an equiripple symetric FIR filter.

Filter 0 has the following specifications:

Filters 1 and 2 share the same module definition, with the following specifications:

The next filtering stage is then executed at 200 kHz. Specifications for filters 3 and 4 are following:

After the second stage of filtering/decimation we will get a complex representaion of the baseband signal. Calculation of the vector magnitude will provide the baseband modulating signal in the form Ac[1 + μm(t)], where Ac is a constant proportional to the pilot signal, and Acμm(t) corresponds to the message signal. The power of the first term indicates the relative power of the radio station, to be used in the future for the AGC implementation. Care must be taken to keep a sampling frequency of 20 kHz at the magnitude stage. The reason is that squaring doubles the bandwidth of the signal.

Finally, a bandpass filter is applied to the magnitude signal. The purpose of this filter is to take away the low frequency components, and refine the filtering of the high frequency component. The specifications of this filter are:

In order to implement a constant bit width at the module interfaces, Matlab is used to calculate the number of bits required for full precision. This calculation is required because Core Generator overestimates this quantity by using only the size of the filter to calculate the output bit width. For this particular design, the results imply to keep bits [36:21] of the output.

As an example, the following are the Core generator parameters for the filters 1 and 2:

• Filter type: Polyphase decimator
• Decimation factor: 20
• Channels: 1
• Taps: 285
• Impulse response: Symmetric
• Coefficient width: 16
• Coefficient type: Signed
• Coefficient buffer type: Block memory
• Input data: 16 bits, signed
• Data buffer type: Block RAM.
• System clock rate: 200 MHz.
• Input sample rate: 4 MHZ
• Registered output.

The designed filter will deliver 41 bit wide output (otuput bits are not configurable in MAC FIR Filter tool), so externally, bits [36:21] are selected. According to the results of the Matlab calculation.

Squaring module design

A multiplier works as a squaring block. As the inputs have the same sign, the output can be configured to be unsigned keeping bits [30:16] in case the multiplier does not replicate the sign bit, or bits [29:15] in case it does. Experimentation with the multiplier is pending to clarify this issue.

Square root module design

Square root module in Core Generator uses CORDIC algorithms to perform the calculation. Unsigned fraction format is used to describe input/output of the module.

AM Stations in the Blacksburg area

The following is a useful summary of AM radio stations in a 40 km perimeter of Blacksburg according to the FCC, usable to test the receiver:

Data obtained from: www.fcc.gov. AM Query in website: http://www.fcc.gov/mb/audio/amq.html

Search parameters:

• State: VA
• Search radius: 40.00 km
• Center lat / lon: N 37 13 48.00 W 80 25 4.00
• Lower Frequency 530 kHz
• Upper Frequency 1700 kHz

-- AdolfoRecio - 24 Apr 2008