OpenFire graphic
OpenFire
Soft Processor


Features
Documentation
Downloads
Craven's Home Page
Features
The OpenFire soft processor is an open source Verilog implementation of the Xilinx MicroBlaze.  Like the MicroBlaze, the OpenFire is a 32-bit RISC processor based on the DLX architecture by Hennessy and Patterson.  The OpenFire was developed by Stephen Craven specifically for configurable array research.  As such, certain features of the MicroBlaze are not currently implemented.  The OpenFire lacks interrupts, exceptions, debugging facilities, and Local Memory Bus and On-chip Peripheral Bus interfaces.  These functions may be added in the future.

The OpenFire follows the three-stage pipeline (fetch, decode, execute) and Havard memory architecture of the MicroBlaze.  All MicroBlaze instructions are supported with the following exceptions.  No floating-point, cache-related, or status register-related instructions are supported.  Furthermore, support for hardware division and barrel shifting is not present at this time, although hardware multiplication is included.

The OpenFire interfaces to memory directly, by-passing the Local Memory Bus interface used by the MicroBlaze.  This reduces the minimum memory requirement from four Block RAMs (BRAM) on the MicroBlaze, to just a single BRAM on the OpenFire.  The Fast Simplex Link (FSL) interface used by the MicroBlaze is implemented on the OpenFire.  Currently only a single FSL port is usable, although an additional port is provided for debugging purposes.  This FIFO-based interface is used to connect multiple OpenFires or to connect an OpenFire to peripherals.




Documentation
The latest documentation can be found in the Downloads section.  As the OpenFire is cycle-accurate to the MicroBlaze for most instructions (excluding multiplication), the Xilinx MicroBlaze Processor Reference Manual is a good source of information.

Pipeline
The three stage pipeline consists of the generic Fetch, Decode and Execute stages.  This simple structure eliminates the need for complex control to introduce pipeline stalls to prevent data hazards.  Like the MicroBlaze, most instructions complete within a single cycle, with the pipeline introducing three cycles of latency.

The Fetch stage interfaces with the instruction memory, providing the memory with the address of the next instruction and registering the fetched instruction.  Each pipeline stage contains a register holding the Program Counter (PC) of the current instruction in that stage.  The PC for the Fetch stage resets to zero and either is updated with the previous PC plus 4 (each instruction word is four bytes) or the PC of any taken branches, as determined by the Execute stage.  The Fetch stage is entirely contained in the fetch.v file.

The Decode stage receives the instruction from the Fetch stage and produces the required control signals for the register file and Execute stage.

The Execute stage performs the requested operation.

Downloads
Version 0.3b of the OpenFire processor is available under the MIT license.  The source code, along with associated utilities and documentation, can be download as a tarball from the link below.  The documentation and utilities assume a Linux environment.

OpenFire v0.3b tarball
(152kB)
OpenFire v0.3b documentation (2.2MB Word format)


Last Updated January 18th, 2006.